1. Field of the Invention
This application relates to electronic design automation, and more particularly to on-chip variation using statistical timing analysis.
2. Description of the Related Art
In general, timing analysis for semiconductor chip designs follows one of two modes. Full statistical libraries can be deployed for cells in a design; however, this approach is computationally expensive and requires that each cell be very well characterized before analysis can be performed. On the other hand, on-chip variation (“OCV”) techniques rely on a global timing margin for a design. While this latter approach is simple and familiar to many designers, the empirically-based margins for a design may fail to correctly capture and benefit from design-specific characteristics that might otherwise conserve layout space, power, and so forth.
There remains a need for timing analysis techniques that provide design-specific results without requiring the overhead of full statistical libraries.